Experimental demonstration of improved analog device performance of nanowire-TFETs. (November 2015)

• Record Type: Journal Article
• Authors: Schulte-Braucks, Christian; Richter, Simon; Knoll, Lars; Selmi, Luca; Zhao, Qing-Tai; Mantl, Siegfried
• Is Part Of: Solid-state electronics. Volume 113(2015)
• Page Start: 179
• Page End: 183
• Publication Date: 2015-11
• Subjects: Strained Si nanowire -- Tunnel-FET -- Subthreshold slope; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2015.05.032
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: We present experimental data on analog device performance of p-type planar- and gate all around (GAA) nanowire (NW) Tunnel-FETs (TFETs) as well as on n-type Tri-Gate-TFETs. A significant improvement of the analog performance by enhancing the electrostatics from planar TFETs to GAA-NW-TFETs with diameters of 20 nm and 10 nm is demonstrated. A maximum transconductance of 122 μS/μm and on-currents up to 23 μA/μm at a gate overdrive of V gt = V d = −1 V were achieved for the GAA NW-pTFETs. Furthermore, a good output current-saturation is observed leading to high intrinsic gain up to 217. The Tri-Gate nTFETs beat the fundamental MOSFET limit for the subthreshold slope of 60 mV/dec and by that also reach extremely high transconductance efficiencies up to 82 V −1 .