Dual Ground Plane EDMOS in 28 nm FDSOI for 5 V power management applications. (November 2015)

• Record Type: Journal Article
• Authors: Litty, Antoine; Ortolland, Sylvie; Golanski, Dominique; Cristoloveanu, Sorin
• Is Part Of: Solid-state electronics. Volume 113(2015)
• Page Start: 42
• Page End: 48
• Publication Date: 2015-11
• Subjects: FD-SOI -- Extended-drain -- MOSFET -- EDMOS -- Back-bias; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2015.05.011
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: A promising high-voltage MOSFET (HVMOS) is experimentally demonstrated in 28 nm Ultra-Thin Body and Buried oxide Fully Depleted SOI technology (UTBB–FDSOI). The Dual Ground Plane Extended-Drain MOSFET (DGP EDMOS) architecture uses the back-gate biasing as an efficient lever to optimize high-voltage performances. The idea is to implement two different ground planes under the device to control separately the electrostatic properties of the channel and the drift regions. We show that the separate biasing of the two ground planes enables the independent tuning of the threshold voltage ( V TH ) as well as the improvement of drain–source breakdown voltage (BV) and specific on-resistance ( R ON . S ). In this work, we explore the electrical characteristics, such as R ON . S and BV, as a function of the back-gate voltage and geometry. We report and discuss encouraging results for 5 V switched mode applications and power management in ultra-thin SOI technology.