FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration. (November 2015)

• Record Type: Journal Article
• Authors: Fenouillet-Beranger, C.; Previtali, B.; Batude, P.; Nemouchi, F.; Cassé, M.; Garros, X.; Tosti, L.; Rambal, N.; Lafond, D.; Dansas, H.; Pasini, L.; Brunet, L.; Deprat, F.; Grégoire, M.; Mellier, M.; Vinet, M.
• Is Part Of: Solid-state electronics. Volume 113(2015)
• Page Start: 2
• Page End: 8
• Publication Date: 2015-11
• Subjects: 3D sequential -- Salicide stability -- FDSOI; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2015.05.005
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.