FPGA-Based Flexible Hardware Architecture for Image Interest Point Detection. (16th July 2015)

• Record Type: Journal Article
• Authors: Hernandez-Lopez, Ana; Torres-Huitzil, Cesar; Garcia-Hernandez, Jose Juan
• Is Part Of: International journal of advanced robotic systems. Volume 12:Number 7(2015)
• Publication Date: 2015-07-16
• Subjects: Interest point detectors -- FPGA -- real-time processing; Robotics -- Periodicals; Robotics; Periodicals; 629.892
• DOI: 10.5772/61058
• Languages: English
• ISSNs: 1729-8806

Abstract

An important challenge in computer vision is the implementation of fast and accurate feature detectors, as they are the basis for high-level image processing analysis and understanding. However, image feature detectors cannot be easily applied in embedded scenarios, mainly due to the fact that they are time consuming and require a significant amount of processing power. Although some feature detectors have been implemented in hardware, most implementations target a single detector under very specific constraints. This paper proposes a flexible hardware implementation approach for computing interest point extraction from grey-level images based on two different detectors, Harris and SUSAN, suitable for robotic applications. The design is based on parallel and configurable processing elements for window operators and a buffering strategy to support a coarse-grain pipeline scheme for operator sequencing. When targeted to a Virtex-6 FPGA, a throughput of 49.45 Mpixel/s (processing rate of 161 frames per second of VGA image resolution) is achieved at a clock frequency of 50 MHz.