Design and analysis of an energy-efficient O-QPSK coherent IR-UWB transceiver with a 0.52° RMS phase-noise fractional synthesizer *Project supported by the National Science and Technology Major Project of China (No. 2011ZX03004-002-01). (March 2018)

• Record Type: Journal Article
• Authors: Ying, Yutong; Lin, Fujiang; Bai, Xuefei
• Is Part Of: Journal of semiconductors. Volume 39:Number 3(2018:Mar.)
• Publication Date: 2018-03
• Subjects: IR-UWB -- O-QPSK modulation -- phase multiplexing -- transmitter -- receiver -- fractional PLL; 2570; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1674-4926/39/3/035003
• Languages: English
• ISSNs: 1674-4926

Abstract

Abstract: This paper explores an energy-efficient pulsed ultra-wideband (UWB) radio-frequency (RF) front-end chip fabricated in 0.18- μ m CMOS technology, including a transmitter, receiver, and fractional synthesizer. The transmitter adopts a digital offset quadrature phase-shift keying (O-QPSK) modulator and passive direct-phase multiplexing technology, which are energy- and hardware-efficient, to enhance the data rate for a given spectrum. A passive mixer and a capacitor cross-coupled (CCC) source-follower driving amplifier (DA) are also designed for the transmitter to further reduce the low power consumption. For the receiver, a power-aware low-noise amplifier (LNA) and a quadrature mixer are applied. The LNA adopts a CCC boost common-gate amplifier as the input stage, and its current is reused for the second stage to save power. The mixer uses a shared amplification stage for the following passive IQ mixer. Phase noise suppression of the phase-locked loop (PLL) is achieved by utilizing an even-harmonics-nulled series-coupled quadrature oscillator (QVCO) and an in-band noise-aware charge pump (CP) design. The transceiver achieves a measured data rate of 0.8 Gbps with power consumption of 16 mW and 31.5 mW for the transmitter and the receiver, respectively. The optimized integrated phase noise of the PLL is 0.52° at 4.025 GHz.