A BFSK and OOK IF demodulation circuit with 2.8 μs settling time and re-configurable image rejection functions for MICS/BCC applications. (July 2018)

• Record Type: Journal Article
• Authors: Gao, Tongqiang; Chen, Zhenxiong; Zhao, Siqi; Yang, Haigang; Cai, Xinxia
• Is Part Of: Journal of semiconductors. Volume 39:Number 7(2018:Jul.)
• Publication Date: 2018-07
• Subjects: low-IF receiver -- VGA -- complex filter -- MICS -- BCC; 2570; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1674-4926/39/7/075001
• Languages: English
• ISSNs: 1674-4926

Abstract

Abstract: A BFSK and OOK IF base-band circuit is provided to implement the low-IF RF receivers for a dual-band MICS/BCC network controller. In order to transfer the massive vital data immediately, the IF circuit is comprised of the fast-settling feed-forward programmable gain amplifier (PGA), a G m – C complex filter, the fixed gain amplifier (FGA) and a 4-input " quadratic sum" demodulator. A novel auto-switched coarse gain-setting method is adopted in the PGA to enhance the reaction speed and narrow the output signal range. Also the PGA does not suffer the same stability constraint as open-loop topologies. The complex filter fulfills the function of image rejection, in which the center frequency and bandwidth can be adjusted individually. The FGA is used to ameliorate the linearity and the 'quadratic sum' demodulator can reduce the overall power consumption. The designed IF circuit is fabricated with SMIC 0.18 μ m CMOS process. The chip area is about 5.36 mm 2 . Measurement results are given to verify the design goals.