Bias Temperature Instability of Normally‐Off GaN MIS‐FET with Low‐Pressure Chemical Vapor Deposition SiNx Gate Dielectric. Issue 10 (10th January 2018)

• Record Type: Journal Article
• Authors: Hua, Mengyuan; Qian, Qingkai; Wei, Jin; Zhang, Zhaofu; Tang, Gaofei; Chen, Kevin J.
• Other Names: Scholz Ferdinand guestEditor.; Schwarz Ulrich guestEditor.; Vescan Andrei guestEditor.; Wernicke Tim guestEditor.
• Is Part Of: Physica status solidi. Volume 215:Issue 10(2018)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2018-01-10
• Subjects: 1/f noise -- bias temperature instability -- GaN -- interfacial protection layers -- MIS‐FET; Solid state physics -- Periodicals; Solids -- Industrial applications -- Periodicals; 530.41
• DOI: 10.1002/pssa.201700641
• Languages: English
• ISSNs: 1862-6300

Abstract

Abstract : In this work, characterizations are conducted to investigate the threshold voltage ( V TH ) stability of the normally‐off GaN metal–insulator–semiconductor (MIS‐) field‐effect transistor (FET) with fully recessed gate structure and highly reliable low‐pressure chemical vapor deposition SiN x gate dielectric. We conducted bias‐temperature instability (BTI) tests under both positive and negative gate bias. We demonstrated the highly stable V TH of the high‐performance MIS‐FETs with small BTI, which benefits from the effective interfacial protection layer. More specifically, combining the BTI tests and drain current 1/ f noise analysis, we present extensive investigation of the physical origins of BTI. According to the experimental evidence and analysis, we ascribe the V TH instability to the trapping/detrapping of the pre‐existing trap states located at the SiN x /GaN interface and/or in the gate dielectric. Abstract : Bias temperature instability (BTI) and related mechanisms are investigated in the E‐mode GaN MIS‐FET with LPCVD‐SiN x gate dielectric. Improved V TH stability is obtained with PECVD‐SiN x interface protection layer, benefiting from the reduced trap density at/near the SiN x /GaN interface. Combining the BTI tests and drain current 1/ f noise analysis, we ascribe the V TH instability to the trapping/detrapping of the pre‐existing trap states located at SiN x /GaN interface and/or in the gate dielectric.