2D modeling based comprehensive analysis of short channel effects in DMG strained VSTB FET. (June 2018)

• Record Type: Journal Article
• Authors: Saha, Priyanka; Banerjee, Pritha; Sarkar, Subir Kumar
• Is Part Of: Superlattices and microstructures. Volume 118(2018)
• Page Start: 16
• Page End: 28
• Publication Date: 2018-06
• Subjects: Short channel effects -- VSTB FET -- Dual gate material -- Strained silicon channel -- DIBL -- HCE; Superlattices as materials -- Periodicals; Microstructure -- Periodicals; Semiconductors -- Periodicals; Superréseaux -- Périodiques; Microstructure (Physique) -- Périodiques; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.spmi.2018.03.070
• Languages: English
• ISSNs: 0749-6036

Abstract

Abstract: The paper aims to develop two dimensional analytical model of the proposed dual material (DM) Vertical Super Thin Body (VSTB) strained Field Effect Transistor (FET) with focus on its short channel behaviour in nanometer regime. Electrostatic potential across gate/channel and dielectric wall/channel interface is derived by solving 2D Poisson's equation with parabolic approximation method by applying appropriate boundary conditions. Threshold voltage is then calculated by using the criteria of minimum surface potential considering both gate and dielectric wall side potential. Performance analysis of the present structure is demonstrated in terms of potential, electric field, threshold voltage characteristics and subthreshold behaviour by varying various device parameters and applied biases. Effect of application of strain in channel is further explored to establish the superiority of the proposed device in comparison to conventional VSTB FET counterpart. All analytical results are compared with Silvaco ATLAS device simulated data to substantiate the accuracy of our derived model. Highlights: Adual material gate (DMG) strained Vertical Super thin body (VSTB) FET is proposed. Modeling of the proposed structure is derived based on2D Poisson's equation and Young's Parabolic Potential Approximation . SCEs significant for device dimension in nanometer regime are demonstrated in terms ofTVRO, HCE andsub threshold slope . Short channel behavior of the device is explored by varyingdevice parameters, Ge mole fraction andapplied biase s. Functional efficiency of the device is established based on performance comparison with conventional VSTB FET counterpart.