Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays *Project supported by the National High Technology and Development Program of China (No. 2012AA012303). (November 2017)

• Record Type: Journal Article
• Authors: Liu, Lintao; Gao, Yuhan; Deng, Jun
• Is Part Of: Journal of semiconductors. Volume 38:Number 11(2017:Nov.)
• Publication Date: 2017-11
• Subjects: reconfigurable -- mixed-signal -- SoC -- FPAA; 85.40.-e; 1205 -- 1265; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1674-4926/38/11/115001
• Languages: English
• ISSNs: 1674-4926

Abstract

Abstract: This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter, digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μ m CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.