Capacitance estimation for InAs Tunnel FETs by means of full-quantum k·p simulation. (June 2015)

• Record Type: Journal Article
• Authors: Gnani, E.; Baravelli, E.; Gnudi, A.; Reggiani, S.; Baccarani, G.
• Is Part Of: Solid-state electronics. Volume 108(2015)
• Page Start: 104
• Page End: 109
• Publication Date: 2015-06
• Subjects: Full-quantum simulation -- Parasitic capacitance -- Tunnel Field-Fffect Transistor (TFET); Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2014.12.005
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: We report for the first time a quantum mechanical simulation study of gate capacitance components in aggressively scaled InAs Nanowire Tunnel Field-Effect Transistors. It will be shown that the gate-drain capacitance exhibits the same functional dependence over the whole V gs range as the total gate capacitance, albeit with smaller values. However, as opposed to the previous capacitance estimations provided by semiclassical TCAD tools, we find that the gate capacitance exhibits a non-monotonic behavior vs. gate voltage, with plateaus and bumps related with energy quantization and subband formation determined by the device cross-sectional size, as well as with the position of channel-conduction subbands relative to the Fermi level in the drain contact. From this point of view, semiclassical TCAD tools seem to be inaccurate for capacitance estimation in aggressively-scaled TFET devices.