A comparative mismatch study of the 20 nm Gate-Last and 28 nm Gate-First bulk CMOS technologies. (June 2015)

• Record Type: Journal Article
• Authors: Rahhal, Lama; Bajolet, Aurelie; Manceau, Jean-Philippe; Rosa, Julien; Ricq, Stephane; Lassere, Sebastien; Ghibaudo, Gerard
• Is Part Of: Solid-state electronics. Volume 108(2015)
• Page Start: 53
• Page End: 60
• Publication Date: 2015-06
• Subjects: Vt -- β -- ID -- Rsd -- Mismatch -- 20 nm Gate-Last -- 28 nm Gate-First -- EOT (Tox); Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2014.12.006
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: In this work the threshold voltage ( Vt ), the current gain factor ( β ), and the drain current ( ID ) mismatch trends for 20 nm Gate-Last bulk CMOS technology integrating High- k /metal gate are investigated. The reported results indicate that the high k /metal Gate-Last technology exhibits a reduced metal gate granularity contribution to the Vt mismatch and good performance in terms of the β mismatch. This study further demonstrates that the ID variability mainly depends on the mismatch trends of Vt and β, and on the contributions of the transconductance divided by the drain current ( Gm / ID ) and the source drain series resistance ( Rsd ) terms. The 20 nm Gate-Last technology exhibits significant improvement in the Vt and β mismatch performance as compared to the 28 nm Gate-First counterpart. The evolution of the Vt and β mismatch parameters, iA Δ Vt and iA Δ β / β, is further analyzed as a function of the electrical oxide thickness EOT ( Tox ) along the technology nodes from 90 nm to 20 nm. A clear trend towards a reduction of the y -axis intercept (i.e. offset) of the linear plot of iA Δ Vt as a function of EOT is observed starting at the 28 nm Gate-First technology, with the offset approaching zero for the 20 nm Gate-Last technology node. This observation point out a considerable decrease of the gate material contribution to mismatch performances.