Contacting graphene in a 200 mm wafer silicon technology environment. (June 2018)

• Record Type: Journal Article
• Authors: Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas
• Is Part Of: Solid-state electronics. Volume 144(2018)
• Page Start: 17
• Page End: 21
• Publication Date: 2018-06
• Subjects: Graphene -- CMOS compatible -- Encapsulation -- Contact resistance -- TLM; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2018.02.010
• Languages: English
• ISSNs: 0038-1101

Abstract

Graphical abstract: Highlights: PECVD of silicon nitride on the graphene was used as the passivation layer. Two approaches for producing contacts to graphene tested with TLM structures. Bulk Ni with a thickness of 200 nm. "Stacked via" with thin Ni instead of Ti compared to standard contacts to Si. "Stacked via" Approach, the values for contact resistances are 200 Ohm µm. Abstract: Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm µm.