Silicon tunnel FET with average subthreshold slope of 55 mV/dec at low drain currents. (May 2018)

• Record Type: Journal Article
• Authors: Narimani, K.; Glass, S.; Bernardy, P.; von den Driesch, N.; Zhao, Q.T.; Mantl, S.
• Is Part Of: Solid-state electronics. Volume 143(2018)
• Page Start: 62
• Page End: 68
• Publication Date: 2018-05
• Subjects: Tunnel FET -- Line-tunneling -- Trap Assisted Tunneling (TAT); Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2018.01.007
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: Silicon pTFET with average SS of 55 mV/dec over two decades of drain current. The device relies on line-tunneling and possible reduction of TAT to achieve steep slopes. Simulations explain the device behavior and help to make suggestions for further improvements. Abstract: In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. The fabricated device shows an on-current of Ion = 2.55 × 10 −7 A/µm at Vds = Von = Vgs − Voff = −0.5 V for an Ioff = 1 nA/µm and an average SS of 55 mV/dec over two orders of magnitude of Id . Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency gm /Id beats the MOSFET performance at low currents.