CSAM: A clock skew-aware aging mitigation technique. Issue 1 (January 2015)

• Record Type: Journal Article
• Authors: Eghbalkhah, Behzad; Kamal, Mehdi; Afzali-Kusha, Ali; Ghaznavi-Ghoushchi, Mohammad Bagher; Pedram, Massoud
• Is Part Of: Microelectronics and reliability. Volume 55:Issue 1(2015)
• Page Start: 282
• Page End: 290
• Publication Date: 2015-01
• Subjects: Aging -- NBTI -- Clock skew -- Lifetime -- Optimization; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2014.09.033
• Languages: English
• ISSNs: 0026-2714

Abstract

Highlights: Proposing a technique to mitigate the NBTI effect on both logic path and clock tree. Focusing the asymmetric aging caused by NBTI on circuits using clock gating schemes. Simultaneous usage of clock skew management, IVC and INC for aging mitigation. Developing two optimization problems to increase the lifetime and reduce the area overhead. Exploiting non-linear non-integer programing to solve the optimization problems. Abstract: In this work, we propose a clock skew-aware aging mitigation (CSAM) technique which considers the effect of asymmetric aging both on logic path and clock tree together. Simultaneous consideration of both parts in the design optimization problem enables us to reduce the area overhead while increasing the lifetime. For the aging mitigation of the logic path, we make use of both internal node control (INC) and input vector control (IVC) techniques while, for the clock tree circuits, a proper choice between NAND or NOR based integrated clock gating (ICG) cell is made. The optimization may be performed based on two objective functions of maximizing lifetime or minimizing the area overhead for a predetermined clock frequency and lifetime. To assess the efficacy of the proposed technique, we compared the lifetimes and area overheads for a set of circuits from ISCAS89 and ITC99 benchmark suites when CSAM and conventional techniques are used. The results, obtained using SPICE simulations for the circuits in a 45-nm technology, reveals that an average lifetime improvement of 34% and an average area overhead reduction of 25.7% for the two objective functions, respectively.