Compact failure modeling for devices subject to electrostatic discharge stresses – A review pertinent to CMOS reliability simulation. Issue 1 (January 2015)

• Record Type: Journal Article
• Authors: Miao, Meng; Zhou, Yuanzhong; Salcedo, Javier A.; Hajjar, Jean-Jacques; Liou, Juin J.
• Is Part Of: Microelectronics and reliability. Volume 55:Issue 1(2015)
• Page Start: 15
• Page End: 23
• Publication Date: 2015-01
• Subjects: Electrostatic discharge (ESD) -- Gate oxide breakdown -- Junction thermal failure -- Thermal network -- Transmission line pulsing (TLP) -- Transient power law (TPL); Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2014.10.015
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: This paper reviews the physical mechanisms and compact modeling approaches of two physical damages in MOS devices induced by electrostatic discharge (ESD) stresses; namely gate oxide breakdown and thermal failures. Theories underlying the failure mechanism are discussed and compact models that can be used to monitor ESD induced gate oxide breakdown and thermal failure are developed. Related work reported in the literature is discussed, and benchmarking of measurement data versus simulation results are included in support of the modeling work.