Improved performance of nanoscale junctionless transistor based on gate engineering approach. Issue 2 (February 2015)

• Record Type: Journal Article
• Authors: Wang, Ying; Shan, Chan; Dou, Zheng; Wang, Li-guo; Cao, Fei
• Is Part Of: Microelectronics and reliability. Volume 55:Issue 2(2015)
• Page Start: 318
• Page End: 325
• Publication Date: 2015-02
• Subjects: Dual-material gate (DMG) -- Double gate (DG) -- Junctionless transistor (JLT) -- DIBL -- ON/OFF current ratio; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2014.11.009
• Languages: English
• ISSNs: 0026-2714

Abstract

Graphical abstract: Highlights: An advanced dual-material-gate junctionless transistor is proposed. It has enhanced the suppression of short channel effects. It has improved the ON/OFF current ratio. It has improved the sub-threshold characteristics. Abstract: In this paper, we propose an effective method to improve the electrical characteristics of dual-material-gate (DMG) junctionless transistor (JLT) based on gate engineering approach, with the example of n-type double gate (DG) JLT with total channel length down to 30 nm. The characteristics are demonstrated and compared with conventional DMG DGJLT and single-material gate (SMG) DGJLT. The results show that the novel DMG DGJLT presents superior subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance ( Gm ), ON/OFF current ratio, and intrinsic delay ( τ ). Moreover, these unique features can be controlled by engineering the length and workfunction of the gate material. In addition, the sensitivities of the novel DMG device with respect to structural parameters are investigated.