Word line program disturbance based data retention error recovery strategy for MLC NAND Flash. (July 2015)

• Record Type: Journal Article
• Authors: Ma, Haozhi; Pan, Liyang; Song, Changlai; Gao, Zhongyi; Wu, Dong; Xu, Jun
• Is Part Of: Solid-state electronics. Volume 109(2015)
• Page Start: 1
• Page End: 7
• Publication Date: 2015-07
• Subjects: NAND Flash -- Reliability -- Retention -- Program disturbance -- Data error recovery; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2015.03.009
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: A WPD based data retention error recovery strategy for MLC NAND Flash is proposed. The strategy exhibits more than 75% retention BER reduction on 2×-nm MLC NAND Flash. The WPD strategy exhibits significant retention error recovery efficiency promotion. Abstract: NAND Flash has been widely used as storage solutions for portable system due to improvement on data throughput, power consumption and mechanical reliability. However, NAND Flash presents inevitable decline in reliability due to scaling down and multi-level cell (MLC) technology. High data retention error rate in highly stressed blocks causes a trend of stronger ECC deployed in system, with higher hardware overhead and spare bits cost. In this paper, a word line program disturbance (WPD) based data retention error recovery strategy, which induces extra electron injection to compensate floating gate electron leakage during long retention time, is proposed to reduce the data retention error rate and improve the retention reliability of highly scaled MLC NAND Flash memories. The proposed strategy is applied on 2×-nm MLC NAND Flash and the device one-year retention error rate after 3 K, 4 K, 5 K and 6 K P/E cycled decreases by 75.7%, 79.3%, 82.3% and 83.3%, respectively.