Embed SRAM IDDOFF fail root cause identification by combination of device analysis and localized circuit analysis. (September 2017)

• Record Type: Journal Article
• Authors: Chen, C.Q.; Ang, G.B.; Ng, P.T.; Rivai, Francis; Ng, H.P.; Quah, A.C.T.; Teo, Angela; Lam, Jeffery; Mai, Z.H.
• Is Part Of: Microelectronics and reliability. Volume 76/77(2017)
• Page Start: 261
• Page End: 266
• Publication Date: 2017-09
• Subjects: Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2017.07.015
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: SRAM is most important component in the logic product. The failure analysis on the SRAM is well developed, but the SRAM IDDOFF analysis is still challenging for the FA engineers. The product has passed the functional test when IDDOFF is measured. This will make electrical fault isolation very difficult. It will be easy to verify the IDDOFF leakage at die level, but difficult or impossible to verify the leakage at the transistor level. In this paper, a SRAM IDDOFF failed unit was analyzed and the conventional EMMI method was employed to do the fault isolation. The hotspot was easily found in the SRAM area. The EMMI signal cover the entire SRAM block, which indicates a gross leakage in the SRAM block. Subsequent layer by layer analysis didn't find any abnormality until contact level. Nanoprobing at contact level also shows nothing abnormal. To understand the leakage path, the SRAM circuit was studied under DC bias condition and combined with a cross-section analysis of the structure. Thus, a suspected leakage path was proposed. Based on this suspect the leakage can only be simulated at M1 level, and then the experiment was redesigned at Via1 level. The leakage was successfully verified by the nanoprobing DC measurement at M1 level. Finally, the TEM analysis confirms the root cause for the IDDOFF fail. Highlights: SRAM with IDDQ fail, DC leakage found and hotspot confirmed inSRAM range. But individual transistors performance shows normal. Circuit analysis under DC bias was conducted and suspected location was isolated. Experiment was re-designed to check the DC performance of SRAM and leakage was verified. TEM confirms the contact over etch in the suspected location