Low‐leakage sub‐threshold 9 T‐SRAM cell in 14‐nm FinFET technology. (7th November 2016)

• Record Type: Journal Article
• Authors: Zeinali, Behzad; Madsen, Jens Kargaard; Raghavan, Praveen; Moradi, Farshad
• Is Part Of: International journal of circuit theory and applications. Volume 45:Number 11(2017:Nov.)
• Page Start: 1647
• Page End: 1659
• Publication Date: 2016-11-07
• Subjects: SRAM -- FinFET -- sub‐threshold operating -- read access time -- leakage reduction; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2280
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: A novel sub‐threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14‐nm FinFET technology is proposed in this paper. The proposed 9 T‐SRAM cell offers an improved access time in comparison to the 8 T‐SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding '0' and an equal leakage current during hold '1' in comparison to the 8 T‐SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8 T‐SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53 MHz at VDD = 270 mV. Copyright © 2016 John Wiley & Sons, Ltd. Abstract : In this paper, we propose a new subthreshold 9 T‐SRAM cell in 14‐nm FinFET technology by which the access time of the memory cell is improved compared to the standard 8 T‐SRAM cell. Furthermore, because of the structure of the cell, the RBL has to be connected to ground during hold and write modes. In this respect, an assist circuit is proposed as well by which the leakage current of the proposed SRAM cell is reduced significantly. Simulation results in Spectre show a leakage reduction of 20% in hold '0' in comparison to the 8 T‐SRAM cell while in hold '1', the leakage current is almost equal to the 8 T‐SRAM cell. Furthermore, the read access time of the proposed cell is reduced by 40% compared to the 8 T‐SRAM cell while write margin and read noise margin of the proposed cell are not degraded.