A high-performance channel engineered charge-plasma-based MOSFET with high-κ spacer. (December 2017)

• Record Type: Journal Article
• Authors: Shan, Chan; Wang, Ying; Luo, Xin; Bao, Meng-tian; Yu, Cheng-hao; Cao, Fei
• Is Part Of: Superlattices and microstructures. Volume 112(2017)
• Page Start: 499
• Page End: 506
• Publication Date: 2017-12
• Subjects: Charge plasma -- High-κ spacer -- Graded channel (GC) -- Fringing field -- Nanoscale MOSFET; Superlattices as materials -- Periodicals; Microstructure -- Periodicals; Semiconductors -- Periodicals; Superréseaux -- Périodiques; Microstructure (Physique) -- Périodiques; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.spmi.2017.10.002
• Languages: English
• ISSNs: 0749-6036

Abstract

Abstract: In this paper, the performance of graded channel double-gate MOSFET (GC-DGFET) that utilizes the charge-plasma concept and a high-κ spacer is investigated through 2-D device simulations. The results demonstrate that GC-DGFET with high-κ spacer can effectively improve the ON-state driving current ( I ON ) and reduce the OFF-leakage current ( I OFF ). We find that reduction of the initial energy barrier between the source and channel is the origin of this I ON enhancement. The reason for the I OFF reduction is identified to be the extension of the effective channel length owing to the fringing field via high-κ spacers. Consequently, these devices offer enhanced performance by reducing the total gate-to-gate capacitance ( C gg ) and decreasing the intrinsic delay (τ). Graphical abstract: Highlights: An enhanced GC-DGFET with high-κ spacer (GC-SP DGFET) is proposed. It has enhanced the ON-state driving current ( I ON ). It has reduced the OFF-leakage current ( I OFF ). It has reduced the total gate-to-gate capacitance ( C gg ) and the intrinsic delay (τ).