A novel high performance nano-scale MOSFET by inserting Si3N4 layer in the channel. (December 2015)

• Record Type: Journal Article
• Authors: Zareiee, Meysam
• Is Part Of: Superlattices and microstructures. Volume 88(2015)
• Page Start: 254
• Page End: 261
• Publication Date: 2015-12
• Subjects: SOI-MOSFET -- Hot carrier effect -- Electric field -- Si3N4 layer; Superlattices as materials -- Periodicals; Microstructure -- Periodicals; Semiconductors -- Periodicals; Superréseaux -- Périodiques; Microstructure (Physique) -- Périodiques; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.spmi.2015.09.017
• Languages: English
• ISSNs: 0749-6036

Abstract

Abstract: In this paper a novel feature of a nano-scale SOI-MOSFET is presented. The goal of the proposed Si3 N4 Layer SOI-MOSFET (SL-SOI) is inserting a Si3 N4 layer in the channel region. This layer in the channel region which has different band gap than silicon causes uniform electric field. So, hot carrier effect and gate current are controlled sufficiently. Moreover, Si3 N4 layer in the channel is extended in the buried oxide to reduce the lattice temperature, and sub-threshold slope. The proposed structure is simulated with two-dimensional ATLAS simulator and compared with conventional SOI-MOSFET. The results show that the new device has a high performance which expands nano-scale MOSFET applications in high temperature. Highlights: A new nano scale MOSFET with Si3 N4 layer in the channel is proposed. The Si3 N4 layer creates a new peak in the electric field profile. Modulated electric field causes low electron temperature. The simulation with ATLAS simulator shows the improved subthreshold slope.