An efficient code compression for MIPS32 processor using dictionary and bit-mask based static and dynamic frequency algorithm. Issue 5 (5th September 2016)

• Record Type: Journal Article
• Authors: Ramani, G.; Geetha, K.
• Is Part Of: Compel. Volume 35:Issue 5(2016)
• Page Start: 1774
• Page End: 1785
• Publication Date: 2016-09-05
• Subjects: Bit mask -- MIPS32 processor -- Static and dynamic frequency-based algorithm -- Code compression technique; Electrical engineering -- Data Processing -- Periodicals; Electrical engineering -- Mathematics -- Periodicals; Electrical engineering -- Periodicals; Electronics -- Data Processing -- Periodicals; Electronics -- Mathematics -- Periodicals; 621.3
• DOI: 10.1108/COMPEL-11-2015-0429
• Languages: English
• ISSNs: 0332-1649

Abstract

Abstract : Purpose: Memory plays a vital role in designing embedded systems. A larger memory can accommodate more and larger applications but increases cost area, as well as energy requirements. Hence, the purpose of this paper is to propose code compression techniques to solve this issue by minimizing the code size of the application program by compressing the instructions with higher static frequency. Design/methodology/approach: The idea is based on the static and dynamic frequency-based algorithm combined with bit mask and dictionary-based algorithm for MIPS32 processor, in order to minimize the code size and improves compression ratio. Findings: The experimental result shows that the proposed system achieves up to 67 percent compression efficiency. Originality/value: The paper presents enhanced versions of the code compression technique.