Highly flexible SRAM cells based on novel tri-independent-gate FinFET. (October 2017)

• Record Type: Journal Article
• Authors: Liu, Chengsheng; Zheng, Fanglin; Sun, Yabin; Li, Xiaojin; Shi, Yanling
• Is Part Of: Superlattices and microstructures. Volume 110(2017)
• Page Start: 330
• Page End: 338
• Publication Date: 2017-10
• Subjects: Tri-independent-gate -- FinFET -- SRAM -- Read stability and speed; Superlattices as materials -- Periodicals; Microstructure -- Periodicals; Semiconductors -- Periodicals; Superréseaux -- Périodiques; Microstructure (Physique) -- Périodiques; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.spmi.2017.08.008
• Languages: English
• ISSNs: 0749-6036

Abstract

Abstract: In this paper, a novel tri-independent-gate (TIG) FinFET is proposed for highly flexible SRAM cells design. To mitigate the read-write conflict, two kinds of SRAM cells based on TIG FinFETs are designed, and high tradeoff are obtained between read stability and speed. Both cells can offer multi read operations for frequency requirement with single voltage supply. In the first TIG FinFET SRAM cell, the strength of single-fin access transistor (TIG FinFET) can be flexibly adjusted by selecting five different modes to meet the needs of dynamic frequency design. Compared to the previous double-independent-gate (DIG) FinFET SRAM cell, 12.16% shorter read delay can be achieved with only 1.62% read stability decrement. As for the second TIG FinFET SRAM cell, pass-gate feedback technology is applied and double-fin TIG FinFETs are used as access transistors to solve the severe write-ability degradation. Three modes exist to flexibly adjust read speed and stability, and 68.2% larger write margin and 51.7% shorter write delay are achieved at only the expense of 26.2% increase in leakage power, with the same layout area as conventional FinFET SRAM cell. Highlights: Two SRAM cell are designed based on proposed Novel tri-independent-gate (TIG) FinFET. Read-write conflict in SRAM can be mitigated through different flexible read modes. 12.16% shorter read delay is achieved in SRAM cell based on single-fin TIG FinFET. 68.2% larger write margin is achieved in SRAM cell based on double-fin TIG FinFET. 51.7% shorter write delay are achieved in SRAM cell based on double-fin TIG FinFET.