20 nm high performance novel MOSHEMT on InP substrate for future high speed low power applications. (September 2017)

• Record Type: Journal Article
• Authors: Ajayan, J.; Subash, T.D.; Kurian, Dheena
• Is Part Of: Superlattices and microstructures. Volume 109(2017)
• Page Start: 183
• Page End: 193
• Publication Date: 2017-09
• Subjects: CMOS -- Interface trap density -- Metal oxide semiconductor high electron mobility transistor (MOSHEMT) -- Quantum well (QW); Superlattices as materials -- Periodicals; Microstructure -- Periodicals; Semiconductors -- Periodicals; Superréseaux -- Périodiques; Microstructure (Physique) -- Périodiques; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.spmi.2017.05.015
• Languages: English
• ISSNs: 0749-6036

Abstract

Abstract: In this work, the DC and RF performance of a 20 nm gate length novel metal oxide semiconductor high electron mobility transistor (MOSHEMT) on InP substrate is studied using Sentaurus TCAD tool. The proposed MOSHEMT device features heavily doped In0.52 Ga0.48 As source/drain regions, delta doped planes on both sides of the In0.7 Ga0.3 As/InAs/In0.7 Ga0.3 As composite channel, a multi layer cap and a very thin layer of HfO2 as gate dielectric. The TCAD simulation results obtained at room temperature using physics based carrier transport model indicates that the 20 nm gate length proposed MOSHEMT device is capable of providing a peak drain current of 2860 mA/mm at VDS = 0.6 V and the peak transconductance obtained for the proposed device is 2890 mS/mm. The fT and fmax obtained for the Lg = 20 nm proposed MOSHEMT on InP substrate are 537 GHz and 631 GHz respectively. At 300 K, the measured Hall mobility of the electrons in the quantum well channel is 11620 cm 2 /V. The on state resistance (RON ), subthreshold swing (SS) and drain induced barrier lowering (DIBL) obtained for the Lg = 20 nm proposed InP-MOSHEMT are 105 Ω μm, 160 mV/dec and 178 mV/V respectively. These devices are undoubtedly, the most suitable candidates for future high speed, low power post silicon logic applications. Highlights: A D-Mode MOSHEMT with heavily doped In0.52 Ga0.48 As S/D regions for future high speed low power post silicon logic applications was proposed. Investigated the impact of strained composite channel and double δ-doping techniques on the DC and RF performance of the proposed MOSHEMT. Investigated the scalability of the proposed MOSHEMT. The factors influencing the ON resistance is analyzed.