Investigation and analysis of dual-k spacer with different materials and spacer lengths for nanowire-FET performance. (October 2017)

• Record Type: Journal Article
• Authors: Ko, Hyungwoo; Kim, Jongsu; Kang, Myounggon; Shin, Hyungcheol
• Is Part Of: Solid-state electronics. Volume 136(2017)
• Page Start: 68
• Page End: 74
• Publication Date: 2017-10
• Subjects: Dual-k spacer -- Parasitic resistance -- Parasitic capacitance -- Intrinsic gate delay -- Inverter -- High-to-low propagation delay; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2017.06.026
• Languages: English
• ISSNs: 0038-1101

Abstract

Graphical abstract: Highlights: Using lower εlk for outer-spacer of dual- k structure can reduce the total capacitance as the level of single εlk spacer. Using higher εhk for inner-spacer of dual- k structure boosts the on-current as the same range of single εhk spacer due to the gate-fringing field effect. At the off-state, most of drain potential is dropped to the outer spacer capacitance and has little effect to the channel. Thus, using lower εlk for outer spacer shows the lower off-current, SSavg and DIBL. Abstract: In this work, dual- k spacer structures are investigated using a variety of materials along the high-k spacer length in detail. It is known that not only the higher permittivity materials of high- k spacer boost the on-current but also lower permittivity materials of low- k spacer effectively reduce the off-current. By compared the results of other various single spacers and dual- k spacers, it is HfO2 /Vacuum dual- k spacer that shows relatively higher ION, ION /IOFF, better immunity of short channel effects and outstanding device performances.