An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs. (August 2017)

• Record Type: Journal Article
• Authors: Ullah, A.; Sanchez, E.; Sterpone, L.; Cardona, L.A.; Ferrer, C.
• Is Part Of: Microelectronics and reliability. Volume 75(2017)
• Page Start: 110
• Page End: 120
• Publication Date: 2017-08
• Subjects: ASIC fault emulation -- Run-time reconfiguration (RTR) -- Fault injection; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2017.06.032
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: FPGA-based emulation of permanent faults in ASICs can considerably improve the fault simulation time compared to traditional software-based approaches. Moreover, a hardware-based solution provides realistic behavior during fault emulation which is often required in safety-critical systems' validation. Previous emulation approaches not only suffers from considerable area ( for instrumentation ) and reconfiguration ( for fault injection ) overheads but also provides limited coverage of the target faults (and fault sites). The latter is due to difficulties in establishing a fault model equivalence when the ASIC structural netlist is passed through the design automation phases of an FPGA. This paper presents a novel approach for fast emulation of permanent faults in ASICs on state-of-the-art dynamically reconfigurable SRAM-based FPGAs while achieving fault model equivalence. Our proposed approach leverages localized run-time in-place Look Up Table (LUT) reconfigurations to avoid the time-consuming bitstream generation process for every ASIC fault. Moreover, the speed of fault injection is enhanced by direct LUT configuration data modification inside a bitstream frame. This results in 17 and 4 times improvements in fault injection speeds over vendor-provided LUT modification libraries and existing partial bitstream based approaches respectively. However, this improvement is achieved at an average 1.2 and 1.1 times degradation in area and delay metrics for the considered mapped circuits which is affordable considering the benefits in terms of the emulation speed.