An improved design and simulation of low-power and area efficient parallel binary comparator. (August 2017)

• Record Type: Journal Article
• Authors: Chua, Chang; Kumar, R.B.N.
• Is Part Of: Microelectronics journal. Volume 66(2017)
• Page Start: 84
• Page End: 88
• Publication Date: 2017-08
• Subjects: Binary comparator -- CMOS technology -- Pass transistor logic -- Power -- Area; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.06.003
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a new low-power and area-efficient parallel binary comparator design based on prefix tree structure. Due to its wide usage in central processing units, optimizing binary comparator for low power applications are need of the hour. A novel EX-OR-NOR gate is used in proposed binary comparator as pre-encoder to reduce area, power and delay. The simulation results performed using CADENCE for CMOS 180 nm – technology. The paper proposes two binary comparator architectures with improved performance. The proposed architecture result in a power reduction upto 25%, area (number of transistors) reduces upto 36% and improves the delay performance 27% compared to existing technique.