Static fault localization of subtle metallization defects using near infrared photon emission microscopy. (June 2017)

• Record Type: Journal Article
• Authors: Quah, A.C.T.; Nagalingam, D.; Moon, S.; Susanto, E.; Ang, G.B.; Neo, S.P.; Lam, J.C.; Mai, Z.H.
• Is Part Of: Microelectronics and reliability. Volume 73(2017)
• Page Start: 76
• Page End: 91
• Publication Date: 2017-06
• Subjects: Photon emission microscopy -- Static fault localization -- Metallization defects -- Hot carrier emission -- Open -- Shorts -- Defect prediction -- Functional failures; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2017.04.010
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: In this paper, two electroluminescence phenomena, which enabled the static electrical fault localization of subtle back-end-of-line metallization defects using near-infrared photon emission microscopy in the logic circuitry and the memory array, are described. In the logic circuitry, through the study of the defect-induced hot carrier emissions from the combinational logic gates, distinctive differences in emission characteristic between open and short defects are identified. Using this defect induced emission characterization approach, together with layout trace and analysis, the type of defect can be predicted. The defect physical location, which yielded no detectable hotspot signal, can also be narrowed down along the long failure net. This allows for the selection of the most appropriate physical failure analysis approach for defect viewing and thus achieving significant reduction in failure analysis cycle time. In the memory array, the weak emission from partially turned-on pass gate transistor is leveraged to localize marginal opens and shorts on the wordline node of the pass-gate transistor. These approaches are applied with great success in the foundry environment to localize yield limiting defects that resulted in SCAN and memory build-in self-test failure, without memory bitmap, diagnostic support or measurable I DD leakage, on advanced technology nodes devices. A discussion on the factors that influence the success rate of this approach is also provided.