A unified analytical drain current model for Double-Gate Junctionless Field-Effect Transistors including short channel effects. (April 2017)

• Record Type: Journal Article
• Authors: Raksharam, ; Dutta, Aloke K.
• Is Part Of: Solid-state electronics. Volume 130(2017)
• Page Start: 33
• Page End: 40
• Publication Date: 2017-04
• Subjects: Accumulation mode -- Double-Gate Junctionless Field-Effect Transistors (DG-JLFETs) -- Drain Induced Barrier Lowering (DIBL) -- Subthreshold Swing (SS) -- Unified model; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2017.01.003
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: Analytical model for drain current of Junctionless FETs developed, including accumulation and hybrid modes of operation. DIBL and carrier mobility and SS degradation effects included, making the model valid for short-channel devices. Using appropriate smoothing functions, unified model developed, valid over the entire range of gate and drain bias. Model results show excellent match with those obtained from TCAD simulations and experimental data. Shows excellent first-order continuity of the drain current with respect to terminal voltages, making it useful for circuit simulation. Abstract: In this paper, a unified analytical model for the drain current of a symmetric Double-Gate Junctionless Field-Effect Transistor (DG-JLFET) is presented. The operation of the device has been classified into four modes: subthreshold, semi-depleted, accumulation, and hybrid; with the main focus of this work being on the accumulation mode, which has not been dealt with in detail so far in the literature. A physics-based model, using a simplified one-dimensional approach, has been developed for this mode, and it has been successfully integrated with the model for the hybrid mode. It also includes the effect of carrier mobility degradation due to the transverse electric field, which was hitherto missing in the earlier models reported in the literature. The piece-wise models have been unified using suitable interpolation functions. In addition, the model includes two most important short-channel effects pertaining to DG-JLFETs, namely the Drain Induced Barrier Lowering (DIBL) and the Subthreshold Swing (SS) degradation. The model is completely analytical, and is thus computationally highly efficient. The results of our model have shown an excellent match with those obtained from TCAD simulations for both long- and short-channel devices, as well as with the experimental data reported in the literature.