Modeling and analysis of sub-surface leakage current in nano-MOSFET under cutoff regime. (February 2017)

• Record Type: Journal Article
• Authors: Swami, Yashu; Rai, Sanjeev
• Is Part Of: Superlattices and microstructures. Volume 102(2017)
• Page Start: 259
• Page End: 272
• Publication Date: 2017-02
• Subjects: Leakage current -- Sub-surface current -- Tunneling -- Nano-MOSFET -- Modeling -- Short channel effects -- Sub-threshold region; Superlattices as materials -- Periodicals; Microstructure -- Periodicals; Semiconductors -- Periodicals; Superréseaux -- Périodiques; Microstructure (Physique) -- Périodiques; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.spmi.2016.12.044
• Languages: English
• ISSNs: 0749-6036

Abstract

Abstract: The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in nano-MOSFET circuits as threshold voltage, channel length, and gate oxide thickness are scaled down to nano-meter range. Precise leakage current valuation and meticulous modeling of the same at nano-meter technology scale is an increasingly a critical work in designing the low power nano-MOSFET circuits. We present a specific compact model for sub-threshold regime leakage current in bulk driven nano-MOSFETs. The proposed logical model is instigated and executed into the latest updated PTM bulk nano-MOSFET model and is found to be in decent accord with technology-CAD simulation data. This paper also reviews various transistor intrinsic leakage mechanisms for nano-MOSFET exclusively in weak inversion, like drain-induced barricade lowering (DIBL), gate-induced drain leakage (GIDL), gate oxide tunneling (GOT) leakage etc. The root cause of the sub-surface leakage current is mainly due to the nano-scale short channel length causing source–drain coupling even in sub-threshold domain. Consequences leading to carriers triumphing the barricade between the source and drain. The enhanced model effectively considers the following parameter dependence in the account for better-quality value-added results like drain-to-source bias ( V DS ), gate-to-source bias ( V GS ), channel length ( L G ), source/drain junction depth (Xj ), bulk doping concentration ( N BULK ), and operating temperature ( T op ). Highlights: The research work models and analyzes the sub-surface leakage current in cut-off regime for bulk driven nano-MOSFETs especially @ 10-nm technology node along with various sub 45-nm technology nodes for accurate results. Different types of leakage currents existing in nano-MOSFET are briefly discussed and successfully simulated on TCAD. Outcomes of the research work is briefly presented through the versatile simulations of the model devices to infer the most appropriate model at nanometer technology nodes. The enhanced model effectively considers the following parameter dependence in the account for better-quality value-added results like drain-to-source bias (VDS ), gate-to-source bias (VGS ), channel length (LG ), source/drain junction depth (Xj ), bulk doping concentration (NBULK ), and operating temperature (Top ).