Process modules for GeSn nanoelectronics with high Sn-contents. (February 2017)

• Record Type: Journal Article
• Authors: Schulte-Braucks, C.; Glass, S.; Hofmann, E.; Stange, D.; von den Driesch, N.; Hartmann, J.M.; Ikonic, Z.; Zhao, Q.T.; Buca, D.; Mantl, S.
• Is Part Of: Solid-state electronics. Volume 128(2017)
• Page Start: 54
• Page End: 59
• Publication Date: 2017-02
• Subjects: GeSn -- MOSFET -- High-k/metal gate -- NiGeSn; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2016.10.024
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: This paper systematically studies GeSn n-FETs, from individual process modules to a complete device. High-k gate stacks and NiGeSn metallic contacts for source and drain are characterized in independent experiments. To study both direct and indirect bandgap semiconductors, a range of 0–14.5 at.% Sn-content GeSn alloys are investigated. Special emphasis is placed on capacitance-voltage (C-V) characteristics and Schottky-barrier optimization. GeSn n-FET devices are presented including temperature dependent I-V characteristics. Finally, as an important step towards implementing GeSn in tunnel-FETs, negative differential resistance in Ge0.87 Sn0.13 tunnel-diodes is demonstrated at cryogenic temperatures. The present work provides a base for further optimization of GeSn FETs and novel tunnel FET devices.