Effect of temperature–bias annealing on the hysteresis and subthreshold behavior of multilayer MoS2 transistors. Issue 11 (15th September 2016)

• Record Type: Journal Article
• Authors: Giannazzo, F.; Fisichella, G.; Piazza, A.; Di Franco, S.; Greco, G.; Agnello, S.; Roccaforte, F.
• Is Part Of: Physica status solidi. Volume 10:Issue 11(2016)
• Page Start: 797
• Page End: 801
• Publication Date: 2016-09-15
• Subjects: MoS2 -- Schottky barriers -- transistors -- annealing -- multilayers; Solid state physics -- Periodicals; 530.4105
• DOI: 10.1002/pssr.201600209
• Languages: English
• ISSNs: 1862-6254

Abstract

Abstract : The transfer characteristics ( I D – V G ) of multilayers MoS2 transistors with a SiO2 /Si backgate and Ni source/drain contacts have been measured on as‐prepared devices and after annealing at different temperatures ( T ann from 150 °C to 200 °C) under a positive bias ramp ( V G from 0 V to +20 V). Larger T ann resulted in a reduced hysteresis of the I D – V G curves (from ∼11 V in the as‐prepared sample to ∼2.5 V after T ann at 200 °C). The field effect mobility (∼30 cm 2 V –1 s –1 ) remained almost unchanged after the annealing. On the contrary, the subthreshold characteristics changed from the common n‐type behaviour in the as‐prepared device to the appearance of a low current hole inversion branch after annealing. This latter effect indicates a modification of the Ni/MoS2 contact that can be explained by the formation of a low density of regions with reduced Schottky barrier height (SBH) for holes embedded in a background with low SBH for electrons. Furthermore, a temperature dependent analysis of the subthreshold characteristics revealed a reduction of the interface traps density from ∼9 × 10 11 eV –1 cm –2 in the as‐prepared device to ∼2 × 10 11 eV –1 cm –2 after the 200 °C temperature–bias annealing, which is consistent with the observed hysteresis reduction.Schematic representation of a back‐gated multilayer MoS2 field effect transistor (left) and transfer characteristics (right) measured at 25 °C on an as‐prepared device and after the temperature–bias annealing at 200 °C under a positive gate bias ramp from 0 V to +20 V. Abstract : The electrical characteristics of MoS2 field effect transistors typically exhibit an n‐type behavior and hysteresis between forward and backward sweep. It is shown that a temperature–bias annealing at 200 °C is effective in decreasing the hysteresis, suggesting a reduction of the trap states at SiO2 /MoS2 interface. Furthermore, p‐type current transport at large negative bias is observed after annealing, indicating a modification of the contact between source/drain and MoS2 .