An architecture and design tool flow for embedding a virtual FPGA into a reconfigurable system-on-chip. (October 2016)

• Record Type: Journal Article
• Authors: Wiersema, Tobias; Bockhorn, Arne; Platzner, Marco
• Is Part Of: Computers & electrical engineering. Volume 55(2016)
• Page Start: 112
• Page End: 122
• Publication Date: 2016-10
• Subjects: Virtual FPGA -- FPGA Overlay -- ZUMA -- ReconOS -- Timing analysis; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2016.04.005
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.