The distributed thermal model of fin field effect transistor. (December 2016)

• Record Type: Journal Article
• Authors: Zubert, Mariusz; Raszkowski, Tomasz; Samson, Agnieszka; Janicki, Marcin; Napieralski, Andrzej
• Is Part Of: Microelectronics and reliability. Volume 67(2016)
• Page Start: 9
• Page End: 14
• Publication Date: 2016-12
• Subjects: Thermal model -- Fin-FET -- Dual-phase-lag -- Fourier-Kirchoff -- Knudsen number; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2016.09.021
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: This paper demonstrates the thermal analysis of the modern Fin-FET transistor manufactured in 12 nm technology node. The analyzed structure is based on the microchip which was developed by Samsung Group and which was applied in modern electronic structures using the 14 nm Samsung Low Power Early technology. The investigated structure consists of the fourfold Fin-FET transistor and contains its ambient. Moreover, the different dynamics of the temperature changing is demonstrated what is the significant issue in power management. The explanation of the character of the crystal lattice, in which distances between nodes are smaller than the average length of the phonon free path, is included. The technical specification of the investigated structure as well as die layers and their material parameters are described. Furthermore, the description of the prepared thermal model is demonstrated. The temperature simulations are carried out using the Finite Difference Method. The simulation results are presented and discussed in detail. Highlights: This paper presents the thermal analysis of the modern Fin-FET 12nm structure. The Dual-Phase-Lag model has been used to considering the microscale effects in heat conduction models at 12nm structure. The estimated temperature changes inside Fin-FET channel using the F-K and DPL models has been presented. The temperature inside Fin-FET channel should be lower than the temperature values obtained using F-K approach. The simulation results show that nano-electronic structures, which are currently applied in modern electronic devices, can operate faster than it is expected.