FPGA LUT delay degradation due to HCI: Experiment and simulation results. (September 2016)

• Record Type: Journal Article
• Authors: Naouss, M.; Marc, F.
• Is Part Of: Microelectronics and reliability. Volume 64(2016)
• Page Start: 31
• Page End: 35
• Publication Date: 2016-09
• Subjects: HCI -- FPGA -- Modelling -- Degradation -- Simulations -- CMOS -- LUT; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2016.07.048
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: Reliability of advanced VLSI circuits becomes more and more important as both product designers and manufactures relentlessly pursue technology advantages and stretch device physical limits to capitalize the consumer electronic market. In this paper, we focus on aging degradation of the Look-Up Table (LUT) on FPGAs. We have characterized the delay degradation of LUT dependent on the duty cycle and the frequency of stress signal. We have identified that the HCI degradation mechanism affects the fall delay more than the rise delay, it is related directly to the frequency stress and independent from the duty cycle. In addition, we built a model of the delay degradation due to HCI depending on switching frequency of stress signal and the aging time. Furthermore, we identified the relation between the effect of each aging transistor and the LUT delay for the HCI aging mechanism. This work is ideal for modelling the LUT aging mechanisms in FPGA.