Cite
HARVARD Citation
Zajac, P. et al. (2016). Impact of floorplanning and thermal vias placement on temperature in 2D and 3D processors. Microelectronics journal. pp. 40-48. [Online].
This is an interim version of our Electronic Legal Deposit Catalogue-eJournals and eBooks while we continue to recover from a cyber-attack.
Zajac, P. et al. (2016). Impact of floorplanning and thermal vias placement on temperature in 2D and 3D processors. Microelectronics journal. pp. 40-48. [Online].