Impact of floorplanning and thermal vias placement on temperature in 2D and 3D processors. (June 2016)

• Record Type: Journal Article
• Authors: Zajac, Piotr; Galicia, Melvin; Maj, Cezary; Napieralski, Andrzej
• Is Part Of: Microelectronics journal. Volume 52(2016)
• Page Start: 40
• Page End: 48
• Publication Date: 2016-06
• Subjects: Multi-core processors -- 3D integrated circuits -- Thermal vias -- Thermal simulation; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.02.013
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In modern integrated circuits, manufactured in nanometer technologies, reducing the hotspot temperature even by several degrees may lead to significant advantages. In particular, in high performance processors, lower temperature translates into fewer reliability concerns, lower cooling costs, the possibility of increasing the operating frequency and extending the device׳s lifetime. Therefore, in this paper we investigate how the positioning of particular processor units in the floorplan (i.e. floorplanning) affects the chip temperatures. We take into consideration 8-and 6-core processors manufactured in 14 nm technology and simulate the temperature distribution for various floorplan designs. It is shown that the difference in maximal temperature for various floorplans can reach even 7.2 K for a typical case. Moreover, the idea for thermal buffers is presented. While it is shown that thermal buffers may not be of great significance in 2D integrated circuits, obtained results indicate that in 3D ICs the combination of thermal buffers and vertical thermal vias may considerably reduce the temperature of the hottest areas.