A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line. (May 2016)

• Record Type: Journal Article
• Authors: Wu, Shang-Lin; Lu, Chien-Yu; Tu, Ming-Hsien; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te
• Is Part Of: Microelectronics journal. Volume 51(2016)
• Page Start: 89
• Page End: 98
• Publication Date: 2016-05
• Subjects: Low power -- Subthreshold SRAM -- Write-assist -- 10T cell; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.02.011
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a disturb-free 10T subthreshold SRAM cell with fully-symmetrical structure and tri-state pre-charge free bit-line (BL). The disturb-free feature facilitates bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The fully-symmetrical cell structure provides balanced margin and performance in advanced strained-silicon and/or FinFET technologies where PMOS strength approaches that of NMOS. The tri-state BL is left floating in standby state to minimize switching activity for energy efficiency. The scheme eliminates the need of BL keeper, provides balanced two-transistor stack read for better read performance, and eases the design and migration. The proposed 10T SRAM cell is demonstrated by 128 kb SRAM macro implemented in 40 nm low-power (40LP) CMOS technology. Measured read and write functionality is demonstrated with VDD down to 0.35 V (~100 mV lower than the threshold voltage). Data is held down to 0.325 V with 2.53 µW standby power. The measured maximum operation frequency is 375 kHz with total power consumption 5.43 µW at 0.35 V.