Drain current model for double-gate tunnel field-effect transistor with hetero-gate-dielectric and source-pocket. (April 2016)

• Record Type: Journal Article
• Authors: Wang, Ping; Zhuang, YiQi; Li, Cong; Jiang, Zhi; Liu, YuQi
• Is Part Of: Microelectronics and reliability. Volume 59(2016)
• Page Start: 30
• Page End: 36
• Publication Date: 2016-04
• Subjects: Tunnel field-effect transistor -- Source-pocket -- Hetero-gate-dielectric -- Analytical model; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2015.09.014
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: In this paper, the application of hetero-gate-dielectric (HGD) and source-pocket (SP) in a double-gate tunnel field-effect transistor (TFET) is proposed for the first time to simultaneously boost the on-current and suppress the ambipolar current. Quasi-two-dimensional (2D) potential and electric field analytical models for the HGD-SP TFET are developed by solving 2D Poisson's equation with matching boundary conditions. Based on the Kane's formula, analytical expression for the band-to-band generation is derived and then used to calculate the drain current. Device Performance for HGD–SP TFET is studied and compared with corresponding HGD TFET and SP TFET. It is demonstrated that the proposed device architecture outperforms the other two devices in terms of on current and ambipolar current. Moreover, the models exactly depict the influence of pocket doping, pocket width, and gate dielectric constant on the surface potential, electric field, and drain current of a HGD–SP TFET. The good accordance between the modeled results and numerical simulation results verifies the accuracy of the proposed models. Highlights: Hetero-gate-dielectric (HGD) and source-pocket (SP) are applied to double-gate tunnel field-effect transistor and a HGD-SP TFET is proposed. By solving 2D Poisson's equation with matching boundary conditions, Quasi-two-dimensional potential and electric field analytical models for the HGD-SP TFET are developed. Drain current model for the proposed HGD-SP TFET is obtained on the basis of Kane's formula. The proposed device architecture outperforms the HGD and SP devices in terms of on current and ambipolar current. The influence of pocket doping, pocket width, and gate dielectric constant on the surface potential, electric field, and drain current of HGD-SP TFET is studied. The model results are compared with simulation results to verify the accuracy of the proposed models.