Heat dissipation assessment of through silicon via (TSV)-based 3D IC packaging for CMOS image sensing. (April 2016)

• Record Type: Journal Article
• Authors: Cheng, Hsien-Chie; Huang, Tzu-Chin; Hwang, Po-Wen; Chen, Wen-Hwa
• Is Part Of: Microelectronics and reliability. Volume 59(2016)
• Page Start: 84
• Page End: 94
• Publication Date: 2016-04
• Subjects: 3D IC -- Through silicon via -- Thermal performance -- Finite element modeling -- Equivalent thermal conductivity model -- Thermal experiments -- Uncertainty analysis; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2015.12.028
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: The study aims at evaluation of the steady-state heat dissipation capability of a high-density through silicon via (TSV)-based three-dimensional (3D) IC packaging technology (briefly termed 3D TSV IC packaging) designed for CMOS image sensing under natural convection through finite element analysis (FEA) and thermal experiments. To enhance modeling and computational efficiency, an effective approach based on FEA incorporating a 3D unit-cell model is proposed for macroscopically and thermally simulating the heterogeneous TSV chips. The developed effective thermal conductivities are compared against those obtained from a rule-of-mixture technique. In addition, the proposed numerical models are validated by comparison with two experiments. Besides, the uncertainties in the input chip power from the specific power supply and in the measured chip junction temperature by the thermal test die are evaluated. Finally, a design guideline for improved thermal performance is provided through parametric thermal study. Highlights: Numerical and experimental study of thermal behavior of 3D TSV IC package is made. SiO2 layer plays a great effect on the effective thermal conductivities of TSV chip. Chip junction temperature of 3D TSV IC package highly depends on power setting. Uniform power setting is ineffective for temperature prediction of very thin chips. Material and area of interposer are the factors most affecting thermal performance.