Design, evaluation and fault-tolerance analysis of stochastic FIR filters. (February 2016)

• Record Type: Journal Article
• Authors: Wang, Ran; Han, Jie; Cockburn, Bruce F.; Elliott, Duncan G.
• Is Part Of: Microelectronics and reliability. Volume 57(2016)
• Page Start: 111
• Page End: 127
• Publication Date: 2016-02
• Subjects: Stochastic computing -- FIR filter -- Throughput per area -- Energy per operation -- Stochastic sequence length -- Fault tolerance; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2015.11.017
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: Stochastic computing utilizes compact arithmetic circuits that can potentially lower the implementation cost in silicon area. In addition, stochastic computing provides inherent fault tolerance at the cost of a less efficient signal encoding. Finite impulse response (FIR) filters are key elements in digital signal processing (DSP) due to their linear phase-frequency response. In this article, we consider the problem of implementing FIR filters using the stochastic approach. Novel stochastic FIR filter designs based on multiplexers are proposed and compared to conventional binary designs implemented using Synopsys tools with a 28-nm cell library. Silicon area, power and maximum clock frequency are obtained to evaluate the throughput per area (TPA) and the energy per operation (EPO). For equivalent filtering performance, the stochastic FIR filters underperform in terms of TPA and EPO compared to the conventional binary design, although the stochastic design shows more graceful degradation in performance with a significant reduction in energy consumption. A detailed analysis is performed to evaluate the accuracy of stochastic FIR filters and to determine the required stochastic sequence length. The fault-tolerance of the stochastic design is compared with that of the binary circuit enhanced with triple modular redundancy (TMR). The stochastic designs are more reliable than the conventional binary design and its TMR implementation with unreliable voters, but they are less reliable than the binary TMR implementation when the voters are fault-free. Highlights: Stochastic FIR filters are proposed by using multiplexers to implement weighted adders and to generate the filter coefficients. A detailed analysis is performed to evaluate the accuracy of the binary and stochastic filters. It provides an estimate of the minimum sequence length required to match the performance of the stochastic filter to that of a conventional filter. A detailed comparison is provided with respect to the fault tolerance of the HWA- and MWA-based stochastic filters. The conventional binary filter and its fault-tolerant triple modular redundancy (TMR) implementation are considered in the comparison.