Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC. (February 2016)

• Record Type: Journal Article
• Authors: Scholz, Mirko; Chen, Shih-Hung; Hellings, Geert; Linten, Dimitri
• Is Part Of: Microelectronics and reliability. Volume 57(2016)
• Page Start: 53
• Page End: 58
• Publication Date: 2016-02
• Subjects: ESD -- Transient-induced latchup -- System-level -- Component-level; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2015.12.009
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: Measurements and mixed-mode simulations are used for the analysis of transient-induced latch-up (TLU) in CMOS IC. The transient interaction of the parasitic SCR with the surrounding off-chip and on-chip circuitry is investigated during positive and negative system-level ESD stress. It is shown, that sufficient on-chip decoupling and an active clamp can improve the TLU robustness of a circuit. Highlights: a parasitic SCR can be triggered even if off-chip decoupling is present transient interaction of the parasitic SCR structure with the surrounding circuitry causes an internal current injection which subsequently latches the circuit a mixed-mode simulation setup is designed which includes the parasitic SCR needs and all passive components with their parasitic additional on-chip decoupling improves the transient-induced latchup robustness