Bias dependence of TID induced single transistor latch for 0.13 μm partially depleted SOI input/output NMOSFETs. (January 2016)

• Record Type: Journal Article
• Authors: Fan, Shuang; Ning, Bingxu; Hu, Zhiyuan; Zhang, Zhengxuan; Bi, Dawei; Peng, Chao; Song, Lei; Dai, Lihua
• Is Part Of: Microelectronics and reliability. Volume 56(2016)
• Page Start: 1
• Page End: 9
• Publication Date: 2016-01
• Subjects: Bias condition -- Buried oxide (BOX) -- Impact ionization -- Single transistor latch -- Silicon-on-insulator (SOI) -- Total ionizing dose (TID); Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2015.10.024
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: In this work, single transistor latch effects induced by total dose irradiation for 0.13 μm partially depleted silicon-on-insulator (PDSOI) n-type metal-oxide-semiconductor field effect transistors (NMOSFETs) were investigated. The front gate transfer characteristics under different bias configurations with forward and reverse gate voltage sweep are characterized to evaluate the latch phenomenon. The results indicate that transmission–gate (TG) bias is the worst case bias for total dose induced latch, and the onset drain voltage required for latchup degrades as the irradiation level increased. Experiments and 2D simulations are performed to analyze the positive trapped charge in the buried oxide (BOX) and its impact on the latch effect. It is demonstrated that the irradiation can enhance the impact ionization and thereby make the device more sensitive to latchup, especially at negative gate voltage. Moreover, the radiation induced coupling effect between the front gate and back gate can make the PDSOI devices in our experiments behave like the fully depleted (FD) ones. Highlights: Latchup in 0.13 μm PDSOI process technology node Latchup for different architecture transistors Three bias conditions TID enhanced DIBL and TID induced couple effects contribute a lot to latchup.