A low power and high gain CMOS LNA for UWB applications in 90 nm CMOS process. Issue 5 (May 2015)

• Record Type: Journal Article
• Authors: Pandey, Sunil; Singh, Jawar
• Is Part Of: Microelectronics journal. Volume 46:Issue 5(2015)
• Page Start: 390
• Page End: 397
• Publication Date: 2015-05
• Subjects: Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2015.01.002
• Languages: English
• ISSNs: 0959-8324

Abstract

<abstract abstract-type="author" id="ab0005"> <title id="sect0005">Abstract</title> <sec> <p id="sp0060">This paper presents a two stage low noise amplifier (LNA) to achieve low power and high gain for 3.1–10.6 GHz ultra-wide band (UWB) applications. Its first stage yields exceptionally wideband input matching because of the input impedance <inline-formula><alternatives><inline-graphic xlink:href="ark:/27927/pgjj2ks269" xlink:type="simple" xmlns:xlink="http://www.w3.org/1999/xlink" /><mml:math altimg="si0020.gif" overflow="scroll" id="d13e596" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:msub><mml:mrow><mml:mi>Z</mml:mi></mml:mrow><mml:mrow><mml:mi mathvariant="italic">in</mml:mi></mml:mrow></mml:msub><mml:mo>=</mml:mo><mml:mn>1</mml:mn><mml:mo>/</mml:mo><mml:msub><mml:mrow><mml:mi>g</mml:mi></mml:mrow><mml:mrow><mml:msub><mml:mrow><mml:mi>m</mml:mi></mml:mrow><mml:mrow><mml:mn>1</mml:mn></mml:mrow></mml:msub></mml:mrow></mml:msub><mml:mo>≈</mml:mo><mml:mn>50</mml:mn><mml:mspace width="0.25em" /><mml:mi mathvariant="normal">Ω</mml:mi></mml:math></alternatives></inline-formula> of the common-gate (CG) input matching transistor. A source degenerated common source (CS) topology with the shunt peaking inductor <inline-formula><alternatives><inline-graphic xlink:href="ark:/27927/pgjj2krv5f" xlink:type="simple" xmlns:xlink="http://www.w3.org/1999/xlink" /><mml:math altimg="si0021.gif" overflow="scroll" id="d13e630" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:msub><mml:mrow><mml:mi>L</mml:mi></mml:mrow><mml:mrow><mml:mi>d</mml:mi><mml:mn>2</mml:mn></mml:mrow></mml:msub></mml:math></alternatives></inline-formula> is designed as the second stage to improve the overall gain response. Using a standard 90 nm CMOS process, the proposed LNA achieves a gain <italic>S</italic><sub>21</sub> approximately equal to 20 dB, while consuming only 4.33 mW power from a 0.6 V supply voltage. With the aid of source degenerated inductor, the simulation results show input return loss <inline-formula><alternatives><inline-graphic xlink:href="ark:/27927/pgjj2krm8m" xlink:type="simple" xmlns:xlink="http://www.w3.org/1999/xlink" /><mml:math altimg="si0022.gif" overflow="scroll" id="d13e655" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:msub><mml:mrow><mml:mi>S</mml:mi></mml:mrow><mml:mrow><mml:mn>11</mml:mn></mml:mrow></mml:msub><mml:mo><</mml:mo><mml:mo>−</mml:mo><mml:mn>10</mml:mn><mml:mspace width="0.25em" /><mml:mi>dB</mml:mi></mml:math></alternatives></inline-formula> in the frequency range of 3.1–9.7 GHz, a noise figure (NF) less than 1.41 dB, and the minimum noise figure (NF<sub><italic>min</italic></sub>) below 1.034 dB in the frequency range of 3.1–10.6 GHz. When a two tone test is performed with a frequency spacing of 2 MHz, the third order input intercept point (IIP3) of −22 dBm is achieved. The other advantages of the proposed LNA are its small group-delay variation and gain variation of ±28 ps and ±0.39 dB, respectively.</p> </sec> </abstract>