A low power and high gain CMOS LNA for UWB applications in 90 nm CMOS process. Issue 5 (May 2015) - Pandey, Sunil; Singh, Jawar
Abstract This paper presents a two stage low noise amplifier (LNA) to achieve low power and high gain for 3.1–10.6 GHz ultra-wide band (UWB) applications. Its first stage yields exceptionally wideband input matching because of the input impedance <alternatives><inline-graphic xlink:href="ark:/27927/pgjj2ks269" xlink:type="simple" xmlns:xlink="http://www.w3.org/1999/xlink" />Zin=1/gm1≈50Ω</alternatives> of the common-gate (CG) input matching transistor. A source degenerated common source (CS) topology with the shunt peaking inductor <alternatives><inline-graphic xlink:href="ark:/27927/pgjj2krv5f" xlink:type="simple" xmlns:xlink="http://www.w3.org/1999/xlink" />Ld2</alternatives> is designed as the second stage to improve the overall gain response. Using a standard 90 nm CMOS process, the proposed LNA achieves a gain S21 approximately equal to 20 dB, while consuming only 4.33 mW power from a 0.6 V supply voltage. With the aid of source degenerated inductor, the simulation results show input return loss <alternatives><inline-graphic xlink:href="ark:/27927/pgjj2krm8m" xlink:type="simple" xmlns:xlink="http://www.w3.org/1999/xlink" />S11<−10dB</alternatives> in the frequency range of 3.1–9.7 GHz, a noise figure (NF) less than 1.41 dB, and the minimum noise figure (NFmin) below 1.034 dB in the frequency range of 3.1–10.6 GHz. When a two tone test is performed with a frequency spacing of 2 MHz, the third order input intercept point (IIP3) of −22 dBm is achieved. The other advantages of the proposed LNA are its small group-delay variation and gain variation of ±28 ps and ±0.39 dB, respectively.