Low VDD and body bias conditions for testing bridge defects in the presence of process variations. Issue 5 (May 2015)

• Record Type: Journal Article
• Authors: Villacorta, Hector; Garcia-Gervacio, Jose; Segura, Jaume; Champac, Victor
• Is Part Of: Microelectronics journal. Volume 46:Issue 5(2015)
• Page Start: 398
• Page End: 403
• Publication Date: 2015-05
• Subjects: Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2015.02.006
• Languages: English
• ISSNs: 0959-8324

Abstract

<abstract abstract-type="author" id="ab0005"> <title id="sect0005">Abstract</title> <sec> <p id="sp0055">Bridge defects are an important manufacturing defect that may escape test causing reliability issues. It has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods lowering test quality. Therefore, advances in test methodologies to enhance bridge detection are required. In this work a Statistical Timing Analysis Framework (STAF) is used to compute the probability of detection of bridge defects for different <italic>V</italic><sub><italic>DD</italic></sub> and RBB values. The detection of the bridge defects of a circuit is computed by the Statistical Fault Coverage (SFC). The STAF allows to capture properly the behavior of the mean and a standard circuit delay when <italic>V</italic><sub><italic>DD</italic></sub> and RBB change. Furthermore, the STAF uses a realistic bridge defect model suitable to consider appropriately the impact of <italic>V</italic><sub><italic>DD</italic></sub> and RBB on delay increase. This methodology is applied to some ISCAS benchmark circuits implemented in a commercial 65 nm CMOS technology. The obtained results of several ISCAS benchmark circuits show clearly that the Statistical Fault Coverage (SFC) increases significantly when <italic>V</italic><sub><italic>DD</italic></sub> is lowered, and increases even more when RBB is applied at Low <italic>V</italic><sub><italic>DD</italic></sub>. The test conditions to improve resistive bridge detection combining Low <italic>V</italic><sub><italic>DD</italic></sub> and Reverse Body Bias (RBB) under a delay based test are determined. It is shown that the impact of RBB on bridge detection improves significantly for a sufficient low value of <italic>V</italic><sub><italic>DD</italic></sub>. The values of Low <italic>V</italic><sub><italic>DD</italic></sub> and RBB can be selected considering the tradeoff between fault coverage and test time penalization.</p> </sec> </abstract>