High accuracy digital aging monitor based on PLL-VCO circuit. (1st January 2015)

• Record Type: Journal Article
• Authors: Zhang, Yuejun; Jiang, Zhidi; Wang, Pengjun; Zhang, Xuelong
• Is Part Of: Journal of semiconductors. Volume 36:Number 1(2015:Jan.)
• Page Start: 015004
• Publication Date: 2015-01-01
• Subjects: Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1674-4926/36/1/015004
• Languages: English
• ISSNs: 1674-4926

Abstract

<abstract xml:lang="en"> <title>Abstract</title> <p>As the manufacturing process is scaled down to the nanoscale, the aging phenomenon significantly affects the reliability and lifetime of integrated circuits. Consequently, the precise measurement of digital CMOS aging is a key aspect of nanoscale aging tolerant circuit design. This paper proposes a high accuracy digital aging monitor using phase-locked loop and voltage-controlled oscillator (PLL-VCO) circuit. The proposed monitor eliminates the circuit self-aging effect for the characteristic of PLL, whose frequency has no relationship with circuit aging phenomenon. The PLL-VCO monitor is implemented in TSMC low power 65 nm CMOS technology, and its area occupies 303.28 × 298.94 μm². After accelerating aging tests, the experimental results show that PLL-VCO monitor improves accuracy about high temperature by 2.4% and high voltage by 18.7%.</p> </abstract>