A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications. (1st January 2015)

• Record Type: Journal Article
• Authors: Zhao, Yuanxin; Gao, Yuanpei; Li, Wei; Li, Ning; Ren, Junyan
• Is Part Of: Journal of semiconductors. Volume 36:Number 1(2015:Jan.)
• Page Start: 015001
• Publication Date: 2015-01-01
• Subjects: Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1674-4926/36/1/015001
• Languages: English
• ISSNs: 1674-4926

Abstract

<abstract xml:lang="en"> <title>Abstract</title> <p>A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper. Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the "pulse-swallowing" phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary. The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached −100 dBc/Hz, and −125 dBc/Hz respectively. The lowest reference spur is −58 dBc.</p> </abstract>