Design of high‐speed low‐power parallel‐prefix adder trees in nanometer technologies. (3rd January 2013)

• Record Type: Journal Article
• Authors: Perri, Stefania; Lanuzza, Marco; Corsonello, Pasquale
• Is Part Of: International journal of circuit theory and applications. Volume 42:Number 7(2014:Jul.)
• Page Start: 731
• Page End: 743
• Publication Date: 2013-01-03
• Subjects: Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.1886
• Languages: English
• ISSNs: 0098-9886

Abstract

<abstract abstract-type="main"> <title>ABSTRACT</title> <p>This paper presents a novel approach to design high‐speed low‐power parallel‐prefix adder trees. Sub‐circuits typically used in the design of parallel‐prefix trees are deeply analyzed and separately optimized. The modules used for computing the group propagate and generate signals have been designed to improve their energy‐delay behavior in an original way. When the ST 45 nm 1 V CMOS technology is used, in comparison with conventional implementations, the proposed approach exhibits computational delay with mean value and standard deviation up to 40% and 48% lower and achieves energy consumption with mean value and standard deviation up to 57% and 40% lower.</p> <p>A 32‐bit Brent‐Kung tree made as proposed here reaches a computational delay lower than 165 ps and dissipates 147.4fJ on average. Copyright © 2013 John Wiley &amp; Sons, Ltd.</p> </abstract>