Layer‐by‐Layer‐Assembled Reduced Graphene Oxide/Gold Nanoparticle Hybrid Double‐Floating‐Gate Structure for Low‐Voltage Flexible Flash Memory. (5th November 2012)

• Record Type: Journal Article
• Authors: Han, Su‐Ting; Zhou, Ye; Wang, Chundong; He, Lifang; Zhang, Wenjun; Roy, V. A. L.
• Is Part Of: Advanced materials. Volume 25:Number 6(2013)
• Page Start: 872
• Page End: 877
• Publication Date: 2012-11-05
• Subjects: Materials -- Periodicals; Chemical vapor deposition -- Periodicals; 620.11
• DOI: 10.1002/adma.201203509
• Languages: English
• ISSNs: 0935-9648

Abstract

<abstract abstract-type="graphical" xml:lang="en"> <title> <x xml:space="preserve">Abstract</x> </title> <p> <bold>A hybrid double‐floating‐gate flexible memory device by utilizing an rGO‐sheet monolayer and a Au NP array as upper and lower floating gates</bold> is reported. The rGO buffer layer acts as a charge‐trapping layer and introduces an energy barrier between the Au NP lower floating gate and the channel. The proposed memory device demonstrates a strong improvement in both field‐effect‐transistor (FET) and memory characteristics. <boxed-text content-type="graphic" position="anchor" orientation="portrait"><graphic position="anchor" mimetype="image" xlink:href="ark:/27927/pgg1ts4cc19" orientation="portrait" xlink:type="simple" xmlns:xlink="http://www.w3.org/1999/xlink" /></boxed-text></p> </abstract>